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Breker Verification Systems Readies RISC-V CoreAssurance and SoCReady SystemVIP for Automated, Certification-level RISC-V Verification Coverage [Yahoo! Finance]
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Test Suite Synthesis AI Technology tracks complex, un-predictable bugs and accelerates coverage of complex, super-scalar, out-of-order microarchitecture pipeline implementations Self-checking content portable across simulation, emulation, post silicon with debug and coverage analysis SAN JOSE, Calif., June 20, 2024 (GLOBE NEWSWIRE) -- Breker Verification Systems , whose product portfolio solves challenges across the functional and system verification process for large, complex semiconductors, today unwrapped its RISC-V CoreAssurance™ and SoCReady™ SystemVIP providing a complete range of automated tests for the entire RISC-V core and SoC verification stack. The first public demonstrations of RISC-V CoreAssurance and SoCReady SystemVIP along with Breker's Trek Test Suite Synthesis portfolio will be held during the 61st Design Automation Conference (DAC) June 24-26 and the RISC-V Summit Europe June 25-27. “The verification of RISC-V cores remains a huge challenge and we applaud
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